Digital single signal line full duplex method and apparatus

ABSTRACT

A driver circuit that permits full duplex transmission of digital data on a single signal line includes means for enabling a receiver of a station having a transmitter and a receiver to ignore outgoing digital signals from the transmitter of the same station and receive incoming signals. The circuit includes means that combine the incoming and outgoing digital signals in the signal line to form a composite multi-level signal which shifts between predetermined amplitude levels and means that recover the incoming digital signals from the composite signal. An offset bias level is added within the receiver signal processing to the transmitter pulse level to reduce noise susceptibility. Using such a circuit a full duplex transmission system of a plurality of stations connected to a common single signal line is provided. Such a system can be operated in a broadcast mode wherein one station can transmit signals to the remainder of stations.

FIELD OF THE INVENTION

This invention relates to a driver circuit for duplexing apparatus andmethods in general and, in particular, apparatus and methods that permitfull duplex transmission of digital data on a single line.

BACKGROUND OF THE INVENTION

In handling analog signals, duplexing methods and apparatus have beenused rather extensively to minimize the number of transmission lines andincrease transmission capacity. Thus, for example, in telephone art,methods entailing use of bridge circuits operated by voice signals havebeen in use extensively to provide full duplex operation. Also,modulation approaches of various nature have been utilized in radio orhigh frequency transmission art to provide a full duplex operation. Ithas been found that these approaches are slow and rather complex. Forexample, the modulation approach tends to be speed limited because thecarrier has to be faster than the signal and requires rather complexmodulation, demodulation and detection circuitry.

Serious attempts have been made to utilize the aforementioned duplexingmethods or apparatus or develop new methods or apparatus in handlingdigital signals. However, to date, as far as the present inventor isaware, such attempts have been successful only to the extent ofproviding full duplex operation using frequency shift modulation orsimilar techniques that require sending carrier signals at higherfrequencies than the data rate. This requires complicated encoding anddecoding circuitry and restricts the data transmission rates to wellbelow the speeds of modern digital circuits. Present techniques forsending high speed digital data in a signal line are restricted to halfduplex operation.

SUMMARY OF THE INVENTION

The foregoing and other shortcomings and problems of the prior art areovercome, in accordance with the present invention, by utilizinginventive driver circuit means that permit the receiver of a stationhaving a transmitter and a receiver to receive an incoming digitalsignal from the transmitter of another station but prevent the receiverfrom receiving digital signals being sent out by the transmitter of thesame station.

According to an aspect of the present invention, a novel method isprovided to permit a full duplex transmission of digital signals over asingle signal line without requiring carrier signals.

According to another aspect of the present invention, novel drivercircuit means that permit a full duplex, synchronous or asynchronous,digital signal transmission over a single signal line is provided.

The basic invention uses a summing resistor as a load resistor acrossthe transmission line at each terminal. The voltage drop across thisresistor is the composite (sum) of the local and remote transmitters. Adifference amplifier subtracts the composite (sum) line voltage from thelocal transmitter voltage (modified with an offset bias) to derive thenet received line voltage. The offset bias reduces noise susceptibility.

The foregoing and other aspects of the present invention will beunderstood more fully from the following detailed description of anillustrative embodiment of the present invention in conjunction withaccompanying drawings, in which:

FIG. 1 shows a block diagram of a transmission system in which thepresent invention may be utilized;

FIG. 2 shows an illustrative driver circuit of the present invention ina block diagram form;

FIG. 3 shows signal waveforms found at certain points in the presentcircuitry that demonstrate its synchronous and asynchronous full duplexoperation.

FIG. 4 shows a detailed illustrative circuit of the type shown in FIG.2; and

FIG. 5 shows a transmission system in a block diagram form utilizing thepresent full duplex transmission methods and apparatus involving aplurality of stations, each having a transmitter and a receiver.

DETAILED DESRIPTION

FIG. 1 shows in a block diagram form a full duplex digital transmissionsystem that comprises a single transmission line or bus 11 connecting afirst station A to a second station B wherein each station includes atransmitter/receiver pair. It is to be understood that "transmitter" and"receiver" mentioned in this specification, are used as genericexpressions to denote many diverse systems and subsystem components,such as teletypewriters, CRT display devices, memories, registers,central processing units and the like that function as a transmitter orreceiver of digital signals. Likewise, a "transmission line" is used asa generic expression to denote a single signal transmission path, suchas a bus interconnecting the stations. Also, the "full duplex digitaltransmission" systems described herein is intended to encompasssynchronous as well as asynchronous transmission systems. Hence, in thiscontext, whether synchronous or asynchronous, at any given moment theremay exist simultaneously outgoing digital signals from station A tostation B and incoming digital signals from station A to station B andthe system can handle the incoming and outgoing digital signalssimultaneously.

In accordance with the present invention, full duplex operation of thetransmission system over a single signal line is rendered possible byusing a driver circuitry of a unique design that applies the outgoingsignal from a transmitter to the signal line, that applies incomingdigital signals from the line to the receiver, and that prevents thereceiver from receiving outgoing digital signals from the transmitter ofthe same station. FIG. 2 illustrates an operational block diagram of thecircuit means that implement the aforementioned full duplex transmissionmethod.

Generally stated, the driver circuit means comprises first and secondswitching means S1 and S2 and a differential amplifier means DAoperatively connected to permit the full duplex operation. The firstswitching means S1 is of a suitable design that applies the outgoingsignal from the transmitter T1 to the single signal line or bus 11. Thesignals in the line 11 are applied at one, x, of two inputs to thedifferential amplifier. Second switch S2 is used to derive an indicatingsignal representing the outgoing digital signal from the transmitter T1.This indicating signal is applied, at the other y, of the two inputs, tothe differential amplifier. The first switch S1 and load impedance RLare used in a very unique manner to generate and apply three level DCvoltage conditions at the input of the differential amplifier DA.

The differential amplifier then compares its two inputs x and y anddetermines from the comparison whether the signals present in line 11are outgoing or incoming digital signals or both, and prevents thereceiver from receiving the outgoing digital signals, but permits it toreceive incoming digital signals from the transmitter T2 of anotherstation B.

The aforementioned capability of the driver circuit can then be readilyused to render a digital transmission system having a plurality ofstations, each station having a transmitter and a receiver operative ina full duplex mode over a single signal line. This means that outgoingand incoming digital signals may exist simultaneously in the signal lineand that the system can transmit and receive them simultaneously.

Referring to the drawings, FIGS. 2 and 3 show digital signals ofconventional format comprised of binary 1s and 0s found in line 11transmitted by the transmitters T1 and T2 of communicating pair ofstations. Illustrative outgoing digital signals N from the transmitterT1 and incoming digital signals M from the transmitter T2, found intransmission line 11, are shown in FIG. 3. These signals appear in theform of voltage signals and this is rendered possible by using a currentswitch for switch S1. Current switch S1 may be of any conventionaldesign that converts its input, that is, the outgoing digital signalsfrom transmitter T1, which may appear in the voltage form into currentsignals. The current signals are then applied to load impedances RL andRL' to provide IR voltage drop. It is to be understood that loadimpedances RL and RL' are intended to represent any suitable combinationof elements that match line impedances and the provides desired voltagedrop thereacross.

The IR drop forms voltage waveforms in digital signals such as thoseshown in FIG. 3. Note that the net composite of the outgoing andincoming signals appearing in the signal line is a scalar or an analogaddition of the two signals. This unique feature rendered possible bythe use of current switch S1 and is demonstrated graphically in FIG. 3;O, shown in a solid line and designed waveform a. Note that waveform ain FIG. 3; O is a composite or algebraic addition of the outgoing andincoming waveforms M and N shown in FIG. 3. This composite waveformappears in line 11 and is also applied to one of the inputs, x, of thedifferential amplifier.

Now another aspect of the present circuit is that it includes a suitablecircuit means, such as a switch means S2 that derives an indicationsignal which appears in a voltage digital form that follows the patternof the outgoing digital signal. In other words, switch S2 is of a designthat provides output digital signals from the input thereof that are thesame as the input in signal format. Hence, it provides a copy of theinput. This is graphically demonstrated by the dotted line b in FIG. 3;O.

To reduce the noise susceptibility of the system the digital signal(shown as waveform b in FIG. 3; O) appearing at input y of differentialamplifier DA has two voltage levels which fall exactly half way betweenthe first and second, and second and third voltage levels appearing onthe line 11. Any noise induced spurious signal must be of a magnitudegreater than 0.4 volts to cause an error to be transmitted to thereceiver R1 by the voltage comparator DA. If the fourth and fifth levelswere not maintained exactly half way between the first, second, andthird levels, a much lower amplitude noise signal would be able totrigger a spurious output from the voltage comparator DA which wouldthen be detected by the receiver R1. For instance, if waveform b shownin FIG. 3; O .[.where.]. .Iadd.were .Iaddend.offset only 0.1 volts abovethe outgoing transmitted signal, a noise induced signal having anamplitude exceeding 0.1 volts would be sufficient to trigger thecomparator DA which would then generate a spurious output signal.

Now the differential amplifier is used to serve its conventionalfunction of comparing the two signals a and b at its two inputs x and yand generate an output, shown in FIG. 3; P. Note that the resultingoutput is a digital signal which is the same as the incoming digitalsignal. An inherent built-in function of the differential amplifiercompares the composite signal (FIG. 3; O) in the line 11 with theindication digital signal and derives its output (FIG. 3; P), which isthe same as the incoming digital signal in the digital form. Theresulting output (FIG. 3; P) may then be applied to the receiver R1 in aconventional manner.

Note that an interesting phenomenon is observed. What the differentialamplifier does, in effect, is that is subtracts in amplitude sense theinput or outgoing digital signals (FIG. 3; M) from the composite signal(FIG. 3; O) in line 11, and the resulting difference (FIG. 3; P) isapplied as its output. This is graphically illustrated in FIG. 3; P.Note that the dotted line b or the indication signal applied to thesecond input is the same in signal format as the outgoing signal andamplitude shifts the composite wave a so that the shift results in theformation of the output wave (FIG. 3; P), which is a reproduction of theincoming digital signal M, shown in FIG. 3.

Another unique and significant phenomenon flowing from the presentcircuit is that it enables the system to full duplex over a singlesignal line synchronously or asynchronously. Synchrononous transmission,where the outgoing and incoming signals are synchronous, that is wherethey are of the same repetition rate and are in phase, is shown above inconnection with FIG. 3. Asynchronous operation entails the situationwhere the incoming digital signals need not have any repetition rate orphase relationship to the outgoing digital signals. In eithersynchronous or asynchronous operation, the present circuit is of adesign that forms a composite wave of the incoming and outgoing digitalsignals and that subtracts a reference signal from the composite wave toform and derive the incoming digital signals and applies them to thereceiver.

FIG. 4 illustrates .[.a.]. specific circuitry that implements thecircuit shown in FIG. 2 functionally described above with reference toFIG. 3. As illustrated in FIG. 4, the switches S1 and S2 may be of anysuitable conventional design, such as emitter coupled logic, as shown,or TTL logic. The outgoing signals from the transmitter T1 are appliedto suitable voltage level shifting means such as a transistor Q1connected to function as a shifter, as illustrated. The switches S1 andS2 may be of an emitter coupled logic, each comprising a pair oftransistors Q2 and Q3, and Q4 and Q5 arranged in a conventional manner.To assure proper operation of the switches, suitable biasing meanssymbolically denoted by resistive elements, r2, r3, and r4 and may beoperatively connected as illustrated. Also, the base electrodes of Q3and Q5 are established at a suitable potential level utilizing anotheractive element, transistor Q6 which is connected to derive the biasingpotential from a potential dividing means comprised of impedanceelements, r5, r7, r8 and r9. The DC potential source for the drivercircuit, V_(CC) and V_(EE) is divided by the resistive elements r7, r8and r9 and Q6 applies the potential so established to the baseelectrodes of Q3 and Q5.

The driver circuit includes a constant current source 13 containing asuitable active element, such as Q7, which derives and applies apredetermined level of current to switch S1 using resistance of apredetermined magnitude for the resistive element r6. Switch S1 is shownas a conventional current switch wherein only one of the two elements,Q4 and Q5, conducts at any given moment. Normally, Q4 is nonconductingin the absence of an enabling potential applied to the base electrodethereof. The potential that drives the Q4 comes from transistor Q1. Q1,as the level shifter, follows the signal potential input. Accordingly,its emitter output follows its input at its base electrode. The shift inthe emitter, in turn, follows the signal form applied to its input atits base electrode. Q2 and Q4 are biased so that they conduct in thepresence of one state, for example, digit 1, but not the other of theoutgoing digital signals.

For example, in the presence of digital signals 1s or high state inputsignals, Q2 and Q4 are conductive. Q2 and Q4 become nonconductive in thepresence of the opposite digital signal or 0s. In short, Q2 and Q4become conductive in the presence of 1s of digital signals andnonconductive in the presence of 0s of digital signals. Thus, 1s and 0sare used as a means to represent the two states of a digital signal andof course, circuit parameters may be changed whereby Q2 and Q4 becomesconductive in the presence of 0s and nonconductive in the presence of1s.

With Q4 of switch S1 conducting, transistors Q4 and Q7 provide currentdrain path for the transmission line 11. Inasmuch as the constantcurrent from the source 13 is drained through the transmission path 11,the voltage at the transmission line is established by the IR dropformed by the line current times the load impedances RL and RL'. StationB is provided with the same circuitry and accordingly the same thingtakes place in station B.

This being the case, referring to the voltage level at the transmissionline, it is evident that when neither the transmitter of station A northe transmitter of station B sends digital signals, then no current ispresent in the transmission line 11. Accordingly, the voltage at thetransmission line is zero volts. The potential at the transmission line11 shifts between two levels when transmitter T1 of station A ortransmitter T2 of station B, but not both, sends a digital signal. Whenboth transmitters send, then the voltage level at the transmission line11 shifts between three levels, as illustrated in FIG. 3; O.

Inputs to differential amplifier DA .[.is.]. .Iadd.are.Iaddend.connected as follows. The .[.inlput.]. .Iadd.input .Iaddend. xis connected to the transmission line 11 via a resistive means r10.Second input means y is coupled to the collector electrode of firsttransistor Q2 of switch S2. Resistor r10 is connected to the first inputterminal so that the signal from first switch S1 arrives at the inputterminal x at the same time as the signal from the second switch S2arrives at the second input terminal y when the transmitter T1 sends outthe signal. In this manner, any spurious output signals, that mayotherwise be generated by the difference in the arrival time of thesignals to input terminals x and y, are eliminated. Obviously, if thetwo switches match in speed and switch at the same time resistor r10 canbe eliminated.

By supplying ground or 0 volts for V_(cc) and -5.2 volts for V_(EE) andproviding appropriate impedances for the various active and passiveelements, it was possible to provide three levels of voltages to thetransmission line, for example, 0 volts, -0.8 volts, and -1.6 volts, andapply to input x of differential amplifier DA and derive two levels ofvoltages, namely -0.4 volts and -1.2 volts, from the output of the firstactive element Q2 of second switch S2 and apply the same to second inputterminal y of differential amplifier DA. Voltages at the transmissionline 11 are, as indicated before, the result of the IR drop establishedby the IR drop across the impedance RL. RL was chosen to match theimpedance of the transmission line itself to provide better energytransfer and minimum signal reflection.

The operation of the specific circuitry illustrated in FIG. 4 followsthe operation of the functional circuitry shown in FIG. 2 and describedin connection with FIG. 3 and hence, will be stated only briefly here.The output of Q2 of the switch S2 shifts the input terminal y ofdifferential amplifier DA between two levels, namely -0.4 and -1.2volts.

The signals in line 11 shift between two levels, namely, 0 and 0.8volts, when either outgoing or incoming digital signals, but not both,are present. The line signal shifts between three levels, namely, 0,-0.8 and -1.6 volts when both outgoing and incoming digital signals of0s and 1s are present.

The differential amplifier compares the two inputs x and y shiftingbetween different levels as indicated by the signal conditions in line11 and Q2 output and produces an output signal which is a reproductionof the incoming digital signal. The outputs so produced are then appliedto the receiver R1.

In summary then, it has been shown that utilizing a novel circuitry ofthe type illustrated in FIG. 2, in a general block diagram form, and ina specific illustrative embodiment in FIG. 4, a digital signaltransmission system can be rendered operative in a full duplex mode,over single signal path 11, synchronously or asynchronously.

FIG. 5 illustrates a transmission system wherein a plurality oftransmitting stations may be operatively coupled to a single signal line51 terminated by impedance means RL and RL' connected at the two endsthereof. Each station may include a transmitter and a receiver and maybe provided with the aforedescribed drive circuitry having correspondingswitches S1_(A), S1_(B) . . . S1_(N), differential amplifiers DA_(A),DA_(B) . . . DA_(N), etc. According to a further aspect of the presentinvention, the unique property of the circuit means, such as illustratedin FIGS. 2 and 4, permits a system such as that shown in FIG. 5 tooperate in a broadcast mode. FIG. 5 illustrates this in that suppose astation, such as station A, sends out a digital signal, then all of theother stations, B . . . N, connected to the transmission line 51 canreceive the signal sent by station A. This is so because thedifferential amplifiers of the other stations, B . . . N, detect thepresence of the signal in the transmission line 51 coming from thetransmitter A and apply it to the corresponding receivers. It can bereadily seen then that by merely either eliminating the transmitters forthe stations B . . . N or utilizing some suitable external controlmeans, the stations B . . . N may be permitted to receive the signalscoming from the Station A but are prevented from sending out any signalsthemselves.

It is also evident from FIG. 5 and from the foregoing description thatany selected pair of stations A . . . N may provide simultaneous two-waycommunication over the same signal line 51. Suitable external controlmeans in the form of a coding scheme or other circuitry (not shown) maybe used to indicate the identity of called and calling stations so thatthey, not the others connected to line 51, communicate with each other.

In summary it has been shown that in accordance with the presentinvention, a novel drive circuitry is provided to permit a transmissionsystem to operate in a full duplex mode, synchronously or asynchronouslyover a single signal path. It has also been shown that such a novelcircuitry comprises two significant features; namely, it is designed toprovide a current mode signal to the transmission line that allows twooppositely going signals to exist simultaneously on the sametransmission line without interference and that it is designed toutilize the outgoing signal from the transmitter to derive a referenceor indication signal and utilize the resulting reference signal toenable the associated receiver to ignore the outgoing digital signalspresent in the transmission line while receiving the incoming digitalsignals in the transmission line sent from the transmitter of anotherstation. It has also been shown that because of its uniquecharacteristics, use of the present circuitry makes it possible tooperate a full duplex transmission system in a .[.boardcast.]..Iadd.broadcast .Iaddend.mode and with appropriate modifications, anypair of communication stations connected to the same single bus line ofsuch a system may communicate with each other and be able to indicatetheir identity.

Various other modifications and changes may be made to the presentinvention from the principles of the invention described above withoutdeparting from the spirit and scope thereof, as encompassed in theaccompanying claims.

What is claimed is:
 1. A digital transmission system comprising:at leasta pair of stations, at least one of said stations having transmittingmeans and receiving means; a single bus transmission signal path forcarrying .[.the.]. incoming and outgoing digital signals and operativelyconnectable to said transmitting and said receiving means.[.;.]..Iadd.,the outgoing digital signals corresponding to a first and a second logicstate; .Iaddend. first means for applying the outgoing digital signalsfrom said transmitting means to said path, said first means includingcurrent source means for supplying a constant current and .[.said.].first switch means operating to supply or cut off said .Iadd.constant.Iaddend.current from said path in accordance with the shifting patternof the outgoing digital signals between its two states; second means forcombining the outgoing digital signals and incoming digital signals insaid path to form a composite signal which shifts between a plurality ofpredetermined amplitude levels; .Iadd.impedance means connected to saidpath for providing IR voltage drops using current from the digitalsignals present in said path, said impedance means providing potentiallevel shifts between first and second level potentials in the presenceof either outgoing or incoming digital signals and potential levelshifts among said first and second level potentials and a third levelpotential in the presence of both the outgoing and the incoming digitalsignals; and .Iaddend. third means for recovering the incoming digitalsignals from the composite signal and applying the recovered incomingdigital signals to said .[.receiver.]. .Iadd.receiving means.Iaddend.,including second switch means, means for operating said second switchmeans in response to the outgoing digital signals from .[.thetransmitter.]. .Iadd.said transmitting means .Iaddend.for generatingdigital indication signals which are the same in signal content as thatof the outgoing digital signals and which shift between fourth and fifthlevel potentials, and comparing means having first and second inputmeans, .Iadd.the .Iaddend.first input means .Iadd.being .Iaddend.forreceiving the composite signal found in said .[.line.]. .Iadd.path.Iaddend.and .Iadd.the .Iaddend.second input means .Iadd.being.Iaddend.for receiving said digital .[.indicating.]. .Iadd.indication.Iaddend.signals .[.and.]..Iadd., said comparing means being forcomparing the composite signal to said digital indication signals and.Iaddend.deriving an output from the comparison in the form of incomingdigital signals from said path.[.; and.]. .[.impedance means connectedto said path for providing IR voltage drops using the current from thedigital signals present in said path, said impedance means providingpotential level shifts between first and second potentials in thepresence of either outgoing or incoming digital signals and potentiallevel shifts among said first and second level potentials and a thirdlevel potential in the presence of both the outgoing and the incomingdigital signals.]..
 2. The system according to claim 1, including meansfor maintaining .[.the amplitude of.]. said fourth and fifth levelpotentials intermediate between said first and second, and second andthird level potentials, respectively, for minimizing susceptibility ofsaid system to noise signals.
 3. The system according to claim 2,including means for .[.generating a.]. .Iadd.maintaining said constant.Iaddend.current of proper magnitude such that said first, second andthird .[.voltage levels.]. .Iadd.level potentials .Iaddend.can bederived across said impedance means to assure that said first and secondswitch means operate consistent with said .[.comparison.]..Iadd.comparing .Iaddend.means .[.input requirements.]..
 4. The systemaccording to claim 3, said system including a plurality of stations,each station having transmitting and receiving means; andmeans forenabling said system to operate in a broadcast mode.
 5. The systemaccording to claim 4, including means for enabling .[.the calling andcalled stations to identify themselves.]. .Iadd.transmitting means fortwo of said plurality of stations for allowing said two stations toreceive digital signals from each other.Iaddend..
 6. A driver circuitcomprising:a signal path; first means for applying an outgoing digitalsignal from a signal source .Iadd.to said signal path.Iaddend., saidfirst means including current switch means for converting said outgoingdigital signal .[.in.]. .Iadd.to .Iaddend.the form of .[.current.].digital .[.signals and impedance means for providing composite IRvoltage drops in said path using incoming and outgoing digital signalcurrents.]. .Iadd.signal currents.Iaddend.; second means for combiningsaid outgoing digital signal and an incoming digital signal in said pathto form a composite signal which shifts between a plurality ofpredetermined amplitude levels.Iadd., said second means includingimpedance means for providing composite IR voltage drops in said pathusing incoming and outgoing digital signal currents.Iaddend.; thirdmeans for recovering said incoming digital signal from said compositesignal, said third means including second switch means for derivingreference voltage signals which shift in amplitude in response to theoutgoing digital .[.signals.]. .Iadd.signal .Iaddend.and means forcomparing said reference voltage signals with said composite IR voltagedrops for deriving the incoming digital .[.signals.]. .Iadd.signal.Iaddend.from the composite signal; and parameters of said currentswitch means, impedance means, and said second switch means are selectedto shift the .[.voltages.]. .Iadd.composite IR voltage drops .Iaddend.insaid path between first and second levels in the presence of .Iadd.the.Iaddend.outgoing or incoming digital .[.signals.]. .Iadd.signal.Iaddend.alone, and between said first and said second level and a thirdlevel in the presence of both signals, and are selected to shift saidreference .[.signal.]. .Iadd.voltage signals .Iaddend.between fourth andfifth levels.
 7. The circuit according to claim 6, wherein said thirdmeans includes means for establishing .[.the amplitude of.]. the fourthlevel .[.voltage.]. intermediate between the first and second .[.voltagelevel amplitudes.]. .Iadd.levels .Iaddend.and the .[.amplitude of the.].fifth level .[.voltage.]. intermediate between the second and third.[.level voltage amplitudes.]. .Iadd.levels.Iaddend..
 8. A method ofoperating a digital transmission system in a full duplex mode over asingle signal line, said system including at least a pair of stations,each station having transmitting sand receiving means, said methodincluding the steps of:applying outgoing digital signals from saidtransmitting means to said signal line.[...]..Iadd.; .Iaddend. combiningthe outgoing digital signals with incoming digital signals in saidsignal line to form a composite signal which shifts between a pluralityof predetermined amplitude levels, said combining step including the.[.steps.]. .Iadd.step .Iaddend.of shifting among .[.the three levelpotentials.]. .Iadd.a first, a second, and a third level potential.Iaddend.in said line to form a composite voltage waveform representingthe combination of the outgoing and incoming digitalsignals.[.,.]..Iadd.; and recovering the incoming digital signals fromsaid composite signal, said recovering step including the steps of.Iaddend.deriving an indication signal from the outgoing digital signalsand using said indication signal to prevent said receiving means forreceiving said outgoing digital signals in said line, shifting theindication signal between fourth and fifth level .[.potential signals.]..Iadd.potentials .Iaddend.representing the outgoing digital signals,comparing the indication signal with the composite voltage waveform, andderiving the incoming digital signals from the comparison thereof.[.;and.]. .[.recovering the incoming digital signals from said compositesignal.]..
 9. The method according to claim 8, including the step ofestablishing said fourth and fifth level .[.potential signals.]..Iadd.potentials .Iaddend.intermediate between said first and second,and second and third level potentials, respectively, to minimize thesusceptibility of the method to noise interference.
 10. The methodaccording to claim 8, wherein said combining step comprises the stepsof:deriving current form digital signals for the outgoing and incoming.Iadd.digital .Iaddend.signals; applying said current form .Iadd.digital.Iaddend.signals to impedance means connected to said line to form thecomposite signal which .[.vary.]. .Iadd.varies .Iaddend.between.Iadd.said .Iaddend.first and second .[.levels.]. .Iadd.level potentials.Iaddend.when either outgoing or incoming digital signals are present,but not both, and .[.vary.]. .Iadd.which varies .Iaddend.among saidfirst and second .[.levels.]. .Iadd.level potentials .Iaddend.and.[.a.]. .Iadd.said .Iaddend.third level .Iadd.potential .Iaddend.whenboth are present; .[.deriving an indication signal voltage that shiftsbetween.]. .Iadd.and wherein said recovering step comprises the stepsof: maintaining said .Iaddend.fourth and fifth .[.levels thatcorresponds to the 0s and 1s of the outgoing digital signals and thatrange.]. .Iadd.level potentials .Iaddend.intermediate between said firstand second, and said second and third .[.levels.]. .Iadd.levelpotentials.Iaddend., respectively; .[.comparing said composite signalsand said reference signal;.]. .[.deriving an output in the form of theincoming digital signals from the comparison thereof;.]. and applyingsaid .[.output of.]. .Iadd.derived incoming digital signals to.Iaddend.said receiving means.
 11. An apparatus for enabling a digitaltransmission system to operate in a full duplex mode over a singlesignal line, said system having at least two stations, each having atransmitter and a receiver, said apparatus comprising:first means forapplying an outgoing digital signal .Iadd.having a first and a secondlogic state .Iaddend.from a transmitter of one of said stations to saidline including first switch means actuatable in response to the presenceof said outgoing digital signal and applying the outgoing digital signalto said line in the form of a current signal; second means for combiningsaid outgoing digital signal and an incoming digital signal in said lineto form a composite signal which shifts between a plurality ofpredetermined amplitude levels; third means for recovering said incomingdigital signal from said composite signal and applying said recoveredincoming digital signal to .[.said receiver.]. .Iadd.a receiver of saidone station.Iaddend., said third means including .[.means responsive tothe outgoing digital signals for generating an indication signalrepresentative of the logic state of the outgoing digital signals, meansinterposed between said line and said receiver of said one station andresponding to said indication signal for enabling said receiver todisregard said outgoing signal,.]. second switch means responsive to theoutgoing digital signal for generating an indication signalrepresentative of the logic state of the outgoing digital signal, andcomparing means having first and second input means, said first inputmeans .Iadd.being .Iaddend.coupled to said line and said second inputmeans .Iadd.being .Iaddend.coupled to .[.the output of.]. said secondswitch means to receive said indication signal, said comparing means.[.including means.]. .Iadd.being .Iaddend.for comparing input signalsapplied to said first and said second input means and preventing said.[.receiving means.]. .Iadd.receiver of said one station .Iaddend.fromreceiving the outgoing digital signal; a constant current source; meanscoupling said constant current source to said first switch means forallowing current from said current source to flow to said signal lineupon actuation of said first switch means; .Iadd.said second meansincluding .Iaddend.impedance means of a predetermined magnitudeconnected to said signal line for establishing an IR voltagethereacross, said IR voltage drop shifting between first and secondlevels when either the outgoing or incoming digital .[.signals are.]..Iadd.signal is .Iaddend.present and shifting among said first andsecond levels and a third level when both are present; said second.[.switching.]. .Iadd.switch .Iaddend.means providing said indicationsignal in the form of a voltage that shifts between a fourth and a fifthlevel .[.voltage.]., said fourth level .[.having an amplitude range.]..Iadd.being .Iaddend.intermediate between said first and second levels,said fifth level .[.having an amplitude range.]. .Iadd.being.Iaddend.intermediate between said second and third levels; and saidcomparing means comparing the .[.potential.]. levels .[.in the twoinputs thereof.]. .Iadd.of the applied input signals .Iaddend.andextracting from the comparison the incoming digital .[.signals.]..Iadd.signal .Iaddend.from said signal line.
 12. An apparatus forenabling a digital transmission system to operate in a full duplex modeover a single signal line, said system having at least two stations,each having a transmitter and a receiver, said apparatuscomprising;first means for applying an outgoing digital signal.Iadd.having a first and a second logic state .Iaddend.from atransmitter of one of said stations to said line including first switchmeans actuatable in response to the presence of said outgoing digitalsignal and applying the outgoing digital signal to said line in the formof a current signal; second means for combining said outgoing digitalsignal and an incoming digital signal in said line to form a compositesignal which shifts between a plurality of predetermined amplitudelevels; third means for recovering said incoming digital signal fromsaid composite signal and applying said recovered incoming digitalsignal to .[.said receiver.]. .Iadd.a receiver of said onestation.Iaddend., said third means including .[.means responsive to theoutgoing digital signals for generating an indication signalrepresentative of the logic state of the outgoing digital signals, meansinterposed between said line and said receiver of said one station, andresponding to said indication signal for enabling said receiver todisregard said outgoing signal,.]. second switch means responsive to theoutgoing digital signal for generating an indication signalrepresentative of the logic state of the outgoing digital signal, andcomparing means having first and second input means, said first inputmeans .Iadd.being .Iaddend.coupled to said line and said second inputmeans .Iadd.being .Iaddend.coupled to .[.the output of.]. said secondswitch means to receive said indication signal, said comparing means.[.including means or.]. .Iadd.being for .Iaddend.comparing inputsignals applied to said first and said second input means and preventingsaid .[.receiving means.]. .Iadd.receiver of said one station.Iaddend.from receiving the outgoing digital signal; a constant currentsource; means coupling said constant current source to said first switchmeans for allowing current from said current source to flow to saidsignal line upon actuation of said first switch means; .Iadd.said secondmeans including .Iaddend.impedance means of a predetermined magnitudeconnected to said signal line for establishing an IR voltage dropthereacross, said IR voltage drop shifting between first and secondlevels when either the outgoing or incoming digital .[.signals are.]..Iadd.signal is .Iaddend.present and shifting among said first andsecond levels and a third level when both are present; said secondswitch means providing said indication signal in the form a voltagesignal that shifts its voltage between .[.the fourth and.]. .Iadd.afourth and a .Iaddend.fifth level representative of the logic state ofthe outgoing digital signal; and said comparing means generating a.[.high level.]. .Iadd.first .Iaddend.output .Iadd.level .Iaddend.when.[.the potential at.]. .Iadd.a level applied to .Iaddend.said firstinput means exceeds that .[.at.]. .Iadd.applied to .Iaddend.said secondinput means and generating a .[.low level.]. .Iadd.second.Iaddend.output .Iadd.level .Iaddend.when .[.the potential at.]. .Iadd.alevel applied to .Iaddend.said second input means exceeds that .[.at.]..Iadd.applied to .Iaddend.said first input means.